WHY TRANSISTORS BURN IN HF POWER AMPLIFIERS
WHY TRANSISTORS BURN IN HF POWER AMPLIFIERS
Victor's R3KR comments are in italics.
Extremely rugged 50-volt LDMOS devices
Capturing the ISM and broadcast markets
White paper
W. Bloem, J. de Boet, H. van Rossum, K. Vennema
During the last two and a half decades, VDMOS transistors have been the workhorses in many ISM and broadcast applications. Now, that era has come to an end due to continuous improvements in Ampleon’s 50 V LDMOS technology.
The BLF18x-XR series of LDMOS devices enables superior reliability and lower system cost, while eliminating the need for hazardous substances associated with VDMOS packages. This new XR series has been specifically designed for RF energy applications in the industrial, scientific and medical (ISM) frequency bands, where ruggedness, stability and reliability are key drivers both in the market and in transistor design. The devices also enable high efficiency FM and VHF-TV broadcast transmitters with superior correctable linearity.
Ampleon’s customers now have access to a portfolio of devices that will meet all design challenges in today’s applications based on continuous wave, pulsed or linear systems. This paper gives an in-depth description of the technology’s features and how they relate to the performance improvements obtained. Application examples will be given using our latest 50 V LDMOS devices, which provide superior performance when compared to older VDMOS and other 50 V LDMOS technologies currently available in the market.
High Voltage LDMOS Technology
Ampleon’s extremely rugged 50 V transistors are processed in an 8-inch CMOS-wafer fab, which has lithography capabilities down to 0.14 μm. The LDMOS process is derived from the C075 CMOS (0.35 μm gate) process with LOCOS isolation. Additions to the C075 process are the source sinker to the substrate, CoSi2 gate silicidation, tungsten shield and mushroom-type drain structure with thick multi-layer AlCu metallization. Figure 1 is a cross section of the VDMOS technology, and Figure 2 shows the cross section of an LDMOS transistor.
Figure 1: Cross-section of a vertical DMOS transmitting transistor. The length of the gate (the channel length) is the plane of the paper, the channel
width is into the plane of the paper.
Figure 2: Schematic cross-section of a state-of-the art LDMOS transistor
There are a number of important differences between the transistors. With a VDMOS transistor the current flows vertically from top to bottom, the backside of the die is the drain, and a high supply voltage will be present during operation. With an LDMOS transistor, the current flows laterally. The source is connected with a P+ sinker to the backside of the wafer, which makes the backside of the die the source connection of the transistor. The lateral construction enables optimization for high voltage operation at RF frequencies by proper drain-engineering. Appropriate doping levels are chosen in combination with the construction of a field plate, using the “resurf” effect [1]. In addition to drain engineering, optimization of the parasitic bipolar was carried out [2], and will be discussed later in this paper.
Technology Comparison
Table 1 shows a comparison between VDMOS (Ampleon’s BLF278), Ampleon’s BLF188XR LDMOS transistor and a competitor device
In the paragraph below a discussion about the relevance of the various parameters in Table 1 in relation to the various applications is given. We can distinguish between two application areas:
• ISM, high to very high power levels, often exposed to high mismatch where stability, ruggedness and reliability are key design parameters
• Broadcast, high to very high peak power levels, where efficiency and exciter corrected linearity are key design parameters
Thermal Resistance
Thermal resistance is the key parameter that is designed to be as low as possible in order to:
1. Ensure low die junction temperatures to ensure long term reliability (TTF)
2.Maximize the power dissipation the device can handle during mismatch conditions. High currentconditions, and thus high dissipation, can occur depending on the application circuit design and the phase angle of the mismatch. This can create very high dissipation levels, which may result in thermal breakdown of the die and transistor. This typically causes complete destruction of the transistor, see Figure 3.
Figure 3: Example of a thermal device failure as a result of high
dissipation
I will give another example of calculation from the article:
Reliability
Mean time to failure (MTTF) is defined as a 10% reduction in current handling capability by 50% of devices within a given sample size. The primary factor in device failure is due to metal electromigration on the die surface.
Please note that the electromigration of metal does not occur instantly, but over time. That is, when you installed the transistor, saw the power and were happy, but the joy may not last long.
Once the average operating conditions for a given application have been determined, the MTTF can be calculated using the thermal resistance value Rth given in the MRFE6VP61K25H product datasheet.
Example: If the desired operating output power is 1100W, at 80% drain efficiency.
• IDrain = 1100W / (80% x 50V) ~ 27.5A
• MRFE6VP61K25H Rth = 0.15°C/W, Case Temp = 80°C
• Power Dissipation = Pdc -- Pout + Pin
• Power Dissipation = 50V x 27.5A -- 1100W + 4W = 279W
• Temperature Rise = 279W x 0.15°C/W = 42°C
• TJ = Trise + TC = 42°C + 80°C = 122°C
Using Figure 12 which calculates MTTF based on IDrain and TJ; IDrain = 27.5A
Please note that the crystal temperature is directly related to the efficiency of the amplifier. For me personally, it becomes clear that the temperature of the copper radiator under the transistor should not exceed +65C. There can be no talk of +85C degrees! When calculating the crystal temperature, we will not be able to take into account the heat transfer from the transistor case to the copper radiator, it seems to me that we need to add 10-15 degrees, since the thermal conductivity of solder or other materials is much worse than copper.
When soldering a transistor, flux is always used (otherwise you can’t tin it), which boils when heated, and cavities are formed - they are always there. Only soldering in a vacuum can minimize the formation of cavities. In serious production, X-ray control is always carried out after installing the transistor.
The transistor case cannot be considered as a radiator, and even the smallest cavity will lead to point heating of the crystal. If one of the millions of transistors fails because of this, this will be the collapse of the entire LDMOS device.
Generally the thermal resistance can be divided into an RTH,J-C (junction to case) part and an RTH,C-HS (case to heat sink) part. The RTH,J-C is specified by the device manufacturer and the RTH,C-HS depends on the material stack used in the circuit design.
A typical setup to measure the thermal resistance is shown in Figure 4.
Figure 4: Typical infrared measurement setup
The setup has an infrared (IR) camera located directly above the device capable of capturing an enlarged junction temperature image of sections of the device. The device is soldered on a copper insert which is clamped between the input and output part of the test circuit. This total system is then clamped on a water-cooled plate. In order to determine the RTH,J-C, the following information is gathered during the measurement.
The dissipated power (PDISS) is a function of drain efficiency (EffD) and the RF output power (POUT). Thermal resistance of a VDMOS transistor is relatively high compared to an LDMOS product as shown in Table 2.
Amongst other reasons, the relatively high RTH,J-C of a VDMOS device is caused by needing an insulating BeO-disk to mount the VDMOS die (back side is the drain which carries the 50 V supply voltage). This increases the RTH,J-C. The thickness of the die also plays a role in the overall RTH. The VDMOS die is about 200 μm thick, as die lapping techniques were not as advanced when the technology was developed. The LDMOS dies, which are also thinner (120 μm) when compared to VDMOS, are mounted directly to the metal flange of the transistor using a eutectic die attach. This eliminates the need for a thermal interface, thus ensuring the lowest possible thermal resistance for LDMOS devices. The layout of the active die areas and pitch between the fingers of the die have been designed for an optimum thermal resistance and temperature profile along the die, as examined during the IR results shown in Figure 5.
Figure 5: BLF188XR Infrared temperature profile
The thermal resistance, sometimes referred to as thermal impedance (Zth), of an LDMOS transistor changes as a function of pulse width (tpulse) and duty cycle (dc). These thermal properties (as a function of pulse width and duty cycle) are recorded during the IR measurements. Figure 6 shows the results for the changes in thermal impedance Zth, where dc = 1 corresponds to continuous wave (CW) operation.
Figure 6: Thermal impedance (Zth) for the BLF188XR as a function of pulse width and duty cycle
Figure 7: BLF188XR TTF curves for 0.1% failure fraction as function of DC current and temperature
A low thermal resistance is important to ensure long-term reliability of the LDMOS device. Figure 7 shows the lifetime in years at 0.1% failure fraction (TTF0.1%) for the BLF188XR as a function of the junction temperature and the drain-source (i.e. supply) current IDS. TTF0.1% should not be confused with MTF50%, which will show much more optimistic figures.
BVDSS (Vertical Breakdown Voltage)
BV DSS is an important transistor design parameter and influences power capability and ruggedness: in particular when there is significant harmonic content in the output voltage waveform. From theory it is known that the output current waveform has significant 2nd harmonic content when the internal current source is terminated with a non-zero 2nd harmonic impedance.
The resulting 2nd harmonic voltage adds to the fundamental waveform and limits the headroom of the fundamental output voltage, thus limiting the RF output power. This effect is shown in Figure 8 for a 108 MHz test circuit with significant harmonic content, i.e. non optimal harmonic termination at circuit level.
Figure 8: A higher BV DSS in the case of a high harmonic content improves the output power and efficiency when the device starts to compress
Two transistors are compared. The first one has a typical BVDSSof 125 V (dashed line) and the other with a typical BV DSS of 150 V (solid line). It can be seen that the device with the 125 V breakdown voltage goes into compression faster. The obtainable output power is lower and, because the transistor goes into avalanche the efficiency is also affected at output power levels close to compression. The benefits of a transistor with a high BVDSS are even greater when the device is tuned for efficiency (high load-line), used in high classes of operation, or when severe mismatches are applied. Depending on the application design, and as a function of the mismatch phase angle, high voltage peaks may occur on the die, which can lead to degradation or destruction of the transistor. It is obvious that for lower operating frequencies, the effect of higher order harmonics becomes more significant and a high BVDSS is more important. The BLF18x-series has a high BV DSS, as determined by the resistivity and thickness of the epi-layer.
Parasitic Bipolar Breakdown
A parasitic NPN transistor is inherently present in every LDMOS transistor, as part of its structure. Figure 9 gives the schematic representation of the LDMOS transistor, including the parasitic NPN transistor and the drain-substrate diode. Figure 10 highlights the location of the parasitic bipolar NPN transistor in the LDMOS structure.
Figure 9: Electrical representation of the LDMOS and the inherently present parasitic bipolar transistor and drain-substrate diode
Figure 10: Parasitic bipolar NPN transistor highlighted in the LDMOS structure
The drain-source diode clamps the voltage across the LDMOS and the parasitic bipolar sinks the excess current to the substrate. For large sink currents, however, the drain-source voltage exceeds the diode breakdown voltage and the parasitic bipolar transistor can be triggered. Large sink currents can be caused by a mismatch event, improper termination of harmonics, or operation in saturation. Triggering of the parasitic bipolar will lead to nearly instantaneous failure of the LDMOS
transistor, an example is shown in Figure 11. This shows that the failure signature only shows a couple of burned fingers, whereas Figure 3 shows much greater destruction when the transistor goes into thermal failure.
Thus, by opening the burnt transistor, we can look and determine the cause of the failure - overheating or the operation of a parasitic bipolar transistor.
Figure 11: Transistor failure signature when the parasitic bipolar transistor has been triggered
Figure 12: Pulse shaping network for TLP test methodology
To make the parasitic bipolar transistor more robust for a triggering event, it has been characterized by a TLP (Transmission Line Pulse) measurement and optimized. The TLP-test is an on-wafer characterization method (see Figure 12) to determine the triggering characteristics of the parasitic bipolar in the LDMOS device. With a short pulse (50 to 200 ns) the “snap-back” I-V characteristic is measured. The pulse shaping C1-R-C2 network formed by TL1, the attenuator TL2 and the 50 Ohm cable to the device under test, is chosen to set the desired pulse rise time, duration and fall time. The supply voltage determines the peak test voltage applied to the device under test. Important parameters to optimize are the base resistance RB (see Figure 9), the gain and the maximum base current of the parasitic bipolar NPN transistor. Once an LDMOS transistor fails, because of a triggered parasitic bipolar, the device often exhibits a low gate-source resistance (< 200 ohms) when measured with an Ohm-meter on the gate of the device. A perfectly good device will show a very high gate-source resistance (> 1 megaohm). Improved drain engineering together with optimizing the robustness of the parasitic bipolar has resulted in Ampleon’s extremely rugged 50 V LDMOS technology.
So, when you see that the gate is broken to the case, then the transistor failed not because of the gate, but because of overheating or a huge number of harmonics of your amplifier.
When the amplifier enters saturation, at this moment there is an increase in harmonics, and the output signal level stops growing or grows very slowly - this can be observed in low-frequency bands. This is a very dangerous mode. Many amplifiers at frequencies of 1.8-3.6 MHz work simply disgustingly, having low efficiency, which confirms the high level of harmonics.
The situation will also be dangerous if the amplifier uses an ALC system to equalize the power level for all bands. Imagine that you tune the ALC system of the transceiver to 14 MHz and see an output power of 2400 W, then go to 1.8 MHz and the ALC will supply more and more power to the amplifier input to achieve the same result - and this may be impossible for this particular amplifier. This will lead to transistor saturation, an increase in the number of harmonics and to the failure of the transistor. Not necessarily immediately, but over time it will definitely happen. I am convinced that the amplifier should be designed so that the gain nonlinearity in the entire HF band is no more than 10%. This is a completely solvable problem without using the ALC system.
On-die Stability Network
Stability and spurious performance are of particular importance when the device is exposed to severe load mismatchconditions. Stability is important for ISM applications where stringent spurious requirements (< -50 dBc) need to be met.
When the transistor is potentially unstable, and when exposed to severe mismatch conditions, spurious products falling above the specification limit can occur. The BLF18x-XR series has on-die stability networks that minimize stability problems. These internal networks, together with a proper application design, will minimize transistor degradation or destruction. The stability measures that need to be taken in application circuit designs with the BLF18x-XR series are much less severe compared to earlier high voltage LDMOS generations, and in some cases can be completely eliminated. For the LDMOS transistor to accomplish this, an on-die RC network is integrated on the gate side of the transistor, involving large capacitance values of several hundred picofarads. This on- die capacitor is realized using a MIM-cap (Metal-Insulating-Metal capacitor)
with nitride dielectric. To guarantee lifetime reliability, Ampleon performs on-die screening of the integrated MIM-caps [3]. Ampleon is the only company in the industry that has enabled on-die screening for its extremely rugged LDMOS technology, which further enhances the reliability of its transistors.
Figure 13: Stability (Mμ-factor) for the BLF188XR (green line), a competitor LDMOS device (black line), and the BLF278 VDMOS transistor (blue line)
Figure 13 shows that the BLF188XR is unconditionally stable (Mμ > 1) down to 40 MHz. Below 40 MHz the device is potentially unstable. In such a case stability measure may need to be implemented at circuit level outside the transistor. The competitor device and the BLF278 VDMOS transistor show a less than desired Mμ-factor. Die layout also plays an important role in device
stability. An improper die layout can even lead to power scaling issues as a result of oscillations. A transistor with stability problems also risks a lower ruggedness performance.
Figure 14: Spectral plot of the BLF188XR (left) and a competitor LDMOS transistor (right) under severe mismatch conditions
Figure 14 shows the spectral purity of the BLF188XR versus a similar competitor LDMOS transistor under the same mismatch conditions and in the same application circuit. The spurious products are minimal in the left plot (BLF188XR), and merely harmonics are shown which can easily be filtered out. The plot on the right (competitor device) shows a much less clean spectrum, without the ability to filter out the spurious products around the carrier.
Ruggedness
Ruggedness of an RF Power transistor is a complex topic. When an LDMOS transistor is exposed to severe mismatch conditions it can be partly damaged, which can result in performance degradation, or in the most extreme situation, the transistor can blow up (see Figure 3 and Figure 11).
Transistor ruggedness is determined by:
• BV DSS
• Breakdown characteristics of the parasitic bipolar transistor
• Power dissipation that the transistor can handle
• Intrinsic transistor stability (see previous paragraph)
• Avalanche energy that the transistor can handle
There are two ways to characterize the ruggedness of a transistor:
• A high VSWR test, using a mismatch unit with a pulsed CW signal, while increasing the supply voltage
• VDS, the RF output power POUT and manipulating the rise/fall time of the pulse
• Determine the avalanche energy of the transistor using an Unclamped Inductor Switching (UIS) test
High VSWR test
Determining transistor ruggedness by applying a mismatch to the application circuit is achieved by connecting a phase unit to the test circuit.
Figure 15: Block diagram ruggedness testing with mismatch unit
The applied VSWR can be reduced by adding an attenuator in front of the phase unit. The resulting VSWR is calculated with the following formula, where S is the desired VSWR.
To achieve a VSWR = 10:1, the required attenuator in front of the (ideal) phase shifter is 0.8715 dB. Please note that it is extremely difficult to create a phase unit with an infinite VSWR for all phases. Any loss in the phase unit results in a reduction of the VSWR from infinity. Typically, the VSWR of a phase unit varies as a function of the phase angle, and a good (practical) phase unit has VSWR values between 65 and 100. To test the ruggedness as determined by the BVDSS and the parasitic bipolar, typically a pulsed CW signal is used. This avoids transistor break-down at maximum allowable dissipation PDISS. The maximum dissipated power due to reaching power dissipation limits can be calculated using the maximum junction temperature (TJ,MAX for the BLF188XR is 225 °C) and the thermal resistance.
For a case temperature of 75 °C under CW conditions, the maximum dissipated power is 1500 W for an RTH,J-C of 0.1 K/W. Typical pulse conditions used at Ampleon are 50 or 100 μs with 10% duty cycle. Fast rise and fall times, in combination with high drain currents and high inductor values in the application circuit, may have a negative impact on the ruggedness because they can generate high voltage spikes arising from L(dI/dt) transients. However, the breakdown voltage of the parasitic bipolar appears to be sufficiently high for most real-world situations. At Ampleon, high VSWR ruggedness testing starts at nominal supply voltage and nominal output power with a VSWR > 65:1 (through all phases). After the devices pass that test, input drive is gradually increased to levels where the device is 5 dB in compression. Once that test is passed, it is repeated, but now at increased supply voltage. Table 3 gives the tests results for the BLF184XR and BLF188XR, for supply voltages (VDS) up to 60 V.
UIS Test to Determine Ruggedness
The UIS test was developed for testing avalanche dependability of switch mode power supply MOSFETS. Power MOSFET devices are rated for a certain maximum BV DSS reverse voltage, and operation of devices at VDS well above the BVDSS breakdown threshold causes the creation and multiplication of electron-hole pairs. This reverse avalanche current flows through the drain-substrate pn-diode causing high dissipation, which leads to thermal destruction. The UIS test determines EAS, the amount of avalanche energy the device can dissipate and absorb in the pn-diode structure. The UIS test is not performed with the device at nominal bias conditions.
Figure 16: Schematic representation of the Unclamped Inductive Switching (UIS) test setup
A simplified schematic of the UIS tester is shown in Figure 16. At the start of the test, switch S1 is closed and the gate of the DUT is energized with a VGS = 10 V (device fully open). The drain current will increase linearly (T1 period, see Figure 17). The instantaneous current is measured with a wideband current probe (not depicted in the diagram). When the drain current reaches the programmed maximum peak current the DUT is turned off by lowering the gate voltage to 0 V and S1 opens, removing the drain power, and closing S2. Current in the inductor continues to flow and causes the voltage across the DUT to rise until the avalanche breakdown voltage is reached. The device begins conducting in avalanche and dissipates the energy that was stored in the inductor. If the device can handle the dissipation, the current decays linearly (T2 period, see Figure 17) until the energy is fully depleted.
Figure 17: Timing diagram of avalanche breakdown test
T1 depicts the charging of the inductor. T2 depicts the avalanche phase
After this the inductor value L is increased to a higher value and the process is repeated until the avalanche voltage VAV breaks down during the T2 period. Upon this event the test is stopped. Now the applied energy, and thus the absorbed single pulse avalanche energy EAS, can be calculated (Equation 4) for the chosen maximum test current IAS.
Figure 18 shows avalanche waveforms for the BLF184XR at an avalanche current of 25 A. The left picture shows the last test before avalanche breakdown happens. The right picture shows avalanche breakdown during T2.
Figure 18: BLF184XR avalanche waveforms just before and during avalanche breakdown
A summary of the avalanche test results using the UIS tester, performed on the BLF278 (VDMOS) and BLF184XR and BLF188XR, can be found in Figure 19. Note that the figures below are for a single section of these push-pull transistors.
Figure 19: Avalanche test results for the BLF278, BLF184XR and BLF188XR for a single transistor section
ESD Diode Enhancement
VDMOS devices did not have any ESD diode protection on the gate side of the transistor. Older 50 V LDMOS devices such as the BLF178P, used a single-sided ESD diode to protect against ESD events on the gate. This single-sided ESD diode had a specification of -0.5 to +11 V. Depending on the application and the application circuit design, it is possible that when the negative cycle of the RF waveform exceeds -0.5 V, the single-sided ESD diode starts to conduct and act as a rectifier (see
Figure 20).
Figure 20: Single-sided ESD diode can cause shift in VBIAS
The amount of rectification is determined by the speed and duration of the signal (pulsed signals and digitally modulated signals have less impact than CW signals). It is also determined by the source impedance (ZSOURCE) of the gate bias (VGS supply) circuit. A high source impedance results in more Δ VBIAS (see Figure 20). A change in VBIAS causes a shift in the operating point of the transistor and can change the mode of operation from Class-C to Class-AB, or even more severe, to Class-A operation. Figure 21 shows the degradation in efficiency at high compression levels for a product without an ESD diode and a product with a single-sided ESD diode.
Figure 21: Degradation of drain efficiency as a result of a VBIAS shift when the single sided ESD diode is present.When there is no ESD diode present, a VBIAS shift will not occur (no rectification)
It is always recommended to have a low ZSOURCE for the VGS-supply. Ampleon typically uses a circuit with a low source impedance. The schematic diagram of this circuit can be found in Figure 22. A detailed description of this VGS-supply circuit can be found in [4].
Figure 22: Low ZSOURCE gate bias circuit
The BLF17x-XR series and BLF18x-XR series use a ‘dual-sided’ ESD diode structure (see Figure 23) with limiting values of -6 to +11 V. On the left the schematic representation of the implemented ESD structure, on the right the leakage currents for both the single-sided as well as dual-sided ESD diode as a function of VGS. The dual-sided ESD diode makes the transistor more suitable for applications that operate in Class-C and for applications that operate the transistor deep in saturation. In the case of a dual-sided ESD diode, no rectification will take place, and the VBIAS remains constant under the most severe conditions.
Figure 23: Schematic representation of the ESD diode implemented in the BLF18x-XR series and leakage characteristics of the single- and dual-sided ESD diode
The BLF18x-XR transistor family is ideal for linear applications, with the internal die layout improved for linear operation. Figure 24 shows the uncorrected linearity for a DVB-T signal at 225 MHz. On the left, the performance for a previous high voltage LDMOS generation is shown. On the right, uncorrected DVB-T shoulder performance is shown for the BLF18x-XR series. Shoulder improvements at lower power levels have been achieved, which makes it easy to pre-correct the transistor.
Figure 24: The BLF188XR (right) is extremely suited to linear applications. On the left an older LDMOS generation showing lower linearity at lower power levels, which can be more difficult to pre-correct
BLF18x-XR Series Reference Designs and Application Highlights
To support design-in activities a large variety of reference designs have been created. Tables 4 and 5 give an overview of the designs that are currently available for the BLF184XR and BLF188XR, respectively. Four BLF188XR reference designs will be discussed in more detail. Extensive test reports including BOM, pc- board layout files and base plate drawings are available.
Table 4: BLF184XR reference designs
Conclusion.
Pay attention to the typical amplifier designs offered by transistor manufacturers in their datasheets. They all have high efficiency, on average about 80%. In order for your amplifier to be reliable, you need to strive for this. High efficiency is the very first and most important parameter that you need to pay attention to, the lifespan of the transistor depends on it.
I will add some thoughts on the topic of adding up powers at HF.
When using modern transistors, adding up powers up to 2 kW is pointless and harmful. I will explain this using the example of two kilowatt that will be added up to reach 2 kilowatts. Each amplifier uses a 9:1 transformer and a balun. All this is fed to the adder. When adding up the powers, we get a resistance of 25 ohms, then, using a 2:1 transformer, we get the resistance we need of 50 ohms. Thus, in the volume of this amplifier we have two 9:1 transformer, two baluns, a combiner and 2:1 transformer. A huge number of ferrites. The largest losses we get in the 2:1 transformer, because such a transformer is a very compromise device with low efficiency. An amplifier with such a circuit solution is obviously doomed to low efficiency. And also, when we add signals with a high level of harmonic content, their level also adds up, grows and the number of harmonics increases. Believe me, I built such amplifiers.
Many will disagree with me, assuring that adding up powers on VHF is quite normal. At high frequencies, amplifiers have a low level of harmonics at the output, because resonant transformers are used, and transistors are selected taking into account the upper operating frequency, therefore, in such amplifiers, harmonics are suppressed to a level of -20-30 dB. Addition of pure signals occurs with a highly efficient resonant adder with minimal losses.
For the HF band, it is much easier to connect transistors in parallel, as EW3MM and many other radio amateurs did in their designs. If you install two 4:1 transformer in series at the output of transistors installed in parallel, you will get a 16:1 transformation and 2000 W of output power. The 4:1 transformer has the lowest possible realizable losses among other transformers. When transistors are connected in parallel, their upper operating frequency and harmonic level decrease. Which has a beneficial effect on efficiency.
The main thing is not to improve cooling with any tricks - small coolers that blow on transformers, liquids and the like (all this will not affect the harmonic level and the amplifier will not become more reliable!), the main thing is to achieve high efficiency.
The translation of the comments was done by machine, in the original and without my comments (bold italics in the text) can be read at the links:
https://www.ampleon.com/documents/white-paper/AMP-WP-2017-0329.pdf
Victor R3KR